The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Aug. 09, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Brian Ermans, 's-Hertogenbosch, NL;

Peter Doliwa, Hamburg, DE;

Gerardus Antonius Franciscus Derks, Dongen, NL;

Wilhelmus Petrus Adrianus Johannus Michiels, Reusel, NL;

Frederik Dirk Schalij, Eindhoven, NL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 18/213 (2023.01); G06F 18/20 (2023.01); G06F 18/211 (2023.01); G06N 3/08 (2023.01);
U.S. Cl.
CPC ...
G06F 18/213 (2023.01); G06F 18/211 (2023.01); G06F 18/285 (2023.01); G06N 3/08 (2013.01);
Abstract

A method is provided for generating a visualization for explaining a behavior of a machine learning (ML) model. In the method, an image is input to the ML model for an inference operation. The input image has an increased resolution compared to an image resolution the ML model was intended to receive as an input. A resolution of a plurality of resolution-independent convolutional layers of the neural network are adjusted because of the increased resolution of the input image. A resolution-independent convolutional layer of the neural network is selected. The selected resolution-independent convolutional layer is used to generate a plurality of activation maps. The plurality of activation maps is used in a visualization method to show what features of the image were important for the ML model to derive an inference conclusion. The method may be implemented in a computer program having instructions executable by a processor.


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