The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Aug. 09, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyungsik Um, Suwon-si, KR;

Jongmin Kim, Suwon-si, KR;

Minsik Oh, Suwon-si, KR;

Donggil Kang, Suwon-si, KR;

Kyungjune Cho, Suwon-si, KR;

Yoon Soo Kim, Suwon-si, KR;

Myunggwan Jeong, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0223 (2013.01); G06F 12/10 (2013.01);
Abstract

An operation method of a storage controller configured to control a non-volatile memory device. The method including receiving a first write command for a first logical address included in a first logical address range corresponding to a first trim bit from an external host, the first trim bit being in an activated state when the first write command is received, performing a first mapping invalidation for the first logical address range in response to the first write command, before the first mapping invalidation is complete, receiving a second write command corresponding to a second logical address included in the first logical address range from the host, skipping a second mapping invalidation corresponding to the second write command, and after the first mapping invalidation is complete, performing a mapping update for the second logical address.


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