Simplified clocking and input/output timing using single data rate link for multiple system-on-chip device

Abstract

In some aspects, an electronic device may include a first system-on-chip (SOC) to generate peripheral data and a single data rate (SDR) clock signal to transport to a second SOC connected to the first SOC by a SoundWire bridge having a single clock line. The electronic device may transport the peripheral data to the second SOC over the SoundWire bridge according to the SDR clock signal carried on the single clock line. For example, to transport the peripheral data to the second SOC over the SoundWire bridge, the first SOC may drive the peripheral data onto a data bus during one or more drive phases associated with the SDR clock signal, and the second SOC may sample the peripheral data from the data bus during one or more bus keeper phases associated with the SDR clock signal. Numerous other aspects are described.