The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Jul. 25, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jong Ho Park, Cheonan-si, KR;

Gyu Ho Kang, Cheonan-si, KR;

Seong-Hoon Bae, Cheonan-si, KR;

Jeong Gi Jin, Seoul, KR;

Ju-Il Choi, Seongnam-si, KR;

Atsushi Fujisaki, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/13 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 25/162 (2013.01); H01L 25/165 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A semiconductor package includes a wiring structure that includes a first insulating layer and a first conductive pattern inside the first insulating layer, a first semiconductor chip disposed on the wiring structure, an interposer that includes a second insulating layer, a second conductive pattern inside the second insulating layer, and a recess that includes a first sidewall formed on a first surface of the interposer that faces the first semiconductor chip and a first bottom surface connected with the first sidewall, where the recess exposes at least a portion of the second insulating layer, a first element bonded to the interposer and that faces the first semiconductor chip inside the recess, and a mold layer that covers the first semiconductor chip and the first element.


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