The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Jul. 01, 2024
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventor:

Er Nie, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H04L 1/004 (2013.01); G06F 2213/0008 (2013.01);
Abstract

A high-speed serial interface includes a physical layer circuit at a transmit end, a monitor, a clock gating circuit, a control bitstream generation circuit, and a random bitstream generation circuit. The monitor is configured to: when no service data is being sent, instruct the clock gating circuit to stop sending a clock signal to partial modules in the physical layer circuit at the transmit end. The control bitstream generation circuit sends a first control bitstream through a serializer/deserializer (SerDes), to indicate that the transmit end has turned off partial modules in the physical layer (PHY) circuit at the transmit end and so on. The random bitstream generation circuit sends a random bitstream.


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