Analog-to-digital converter circuit for masking a system clock signal and an image sensor including the same

Abstract

An image sensor including: a pixel array including first to N-th pixel circuits to generate first to N-th pixel signals; an ADC connected to the pixel circuits; a system clock generator to generate a system clock signal; an internal clock generator to generate first to N-th clock signals and (N+1)-th to 2N-th clock signals based on the system clock signal; a ramp generator to generate first to N-th ramp signals based on the first to N-th clock signals; and a counter clock generator to generate first to N-th counter clock signals based on the (N+1)-th to 2N-th clock signals, the ADC includes: a comparator to generate first to N-th comparison signals based on comparison operations of the first to N-th pixel signals and the first to N-th ramp signals; and a counter to generate first to N-th digital signals based on the comparison signals and the counter clock signals.