The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Sep. 30, 2024
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Tak Ying Wong, Singapore, SG;

Hua Beng Chan, Singapore, SG;

Yun Da Bryan Seah, Mountain View, CA (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); G06F 1/08 (2006.01);
U.S. Cl.
CPC ...
H03K 3/037 (2013.01); G06F 1/08 (2013.01);
Abstract

A fast approach to switching between first and second asynchronous clock signals with reduced latency is provided. When the clock select signal indicates a switch from the first clock signal to the second clock signal, the switch is not made immediately. Instead a blanking signal is generated to suppress the glitch before switching clocks internally. The start of the blanking signal is based on the last falling edge of the internal clock signal before the switch and the end of the blanking signal is based on the first falling edge of the internal clock signal after the switch. The first falling edge is the falling edge of the glitch. The glitchy internal clock is logically combined with the blanking signal to generate an output clock signal that is glitch-free.


Find Patent Forward Citations

Loading…