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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12613829 B1

PDFFull Text
Date of Patent:
Apr. 28, 2026

Filed:

Nov. 16, 2022

Method and system to update weight and bias in partitioned on-chip memory in an inference engine with multiple processing tiles

Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Harri Hakkarainen, Los Gatos, CA (US);

Chia-Hsin Chen, San Jose, CA (US);

Derek Jason Chickles, San Jose, CA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:

Abu Zar Ghaffari

Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 12/02 (2006.01); G06F 15/78 (2006.01); G06N 5/04 (2023.01); G06N 20/00 (2019.01); G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 15/7839 (2013.01); G06F 9/5016 (2013.01); G06F 12/0238 (2013.01); G06F 15/785 (2013.01); G06N 5/04 (2013.01); G06F 8/453 (2013.01); G06N 20/00 (2019.01);
Abstract

A system includes a first and a second processing tiles including a first and a second processing elements and on-chip memory (OCMs) respectively. The first and the second OCM are partitioned. A first partition of the first OCM receives and locally stores a first and a second set of data associated with a first operation and a second operations respectively and accessed by the first processing element for processing the first and the second operations. The second OCM receives and locally stores a third set of data associated with a third operation for access by the second processing element for processing the third operation. The first processing tile processes the first operation based on the first set of data as the second processing element is processing the third operation based on the third set of data while a fourth set of data is being received by the first processing tile.

Find Patent Forward Citations

Hakkarainen, Harri. (2026). Method and system to update weight and bias in partitioned on-chip memory in an inference engine with multiple processing tiles (U.S. Patent No. 12613829). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12613829

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