The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2026
Filed:
Aug. 30, 2022
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventor:
Dong Sop Lee, Icheon-si, KR;
Assignee:
SK HYNIX INC., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 13/4221 (2013.01); H01L 25/0652 (2013.01);
Abstract
A device for implementing a storage architecture includes a front-end chip configured to perform first interfacing with a first device, and a plurality of back-end chips configured to perform second interfacing with second devices. The front-end chip includes front-end links for communication with the plurality of back-end chips, and the plurality of back-end chips include back-end links for communication with the front-end links.
Lee, Dong. (2026). Devices using chiplet based storage architectures (U.S. Patent No. 12613814). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12613814
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile