The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2026

Filed:

Sep. 05, 2023
Applicant:

Luminous Computing, Inc., Santa Clara, CA (US);

Inventors:

Mitchell A Nahmias, Santa Clara, CA (US);

Michael J. Hochberg, New York, NY (US);

Thomas W. Baehr-Jones, Arcadia, CA (US);

Ari Novack, New York, NY (US);

David Cureton Baker, Austin, TX (US);

Matthew Chang, Santa Clara, CA (US);

Lei Wang, Santa Clara, CA (US);

Matthew Streshinsky, Taos, NM (US);

Wuchun Wu, Santa Clara, CA (US);

Hamidreza Nahavandi, Santa Clara, CA (US);

Brian West, Santa Clara, CA (US);

Assignee:

Luminous Computing, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/02 (2006.01); H04B 10/25 (2013.01); H04B 10/40 (2013.01);
U.S. Cl.
CPC ...
G06F 13/1615 (2013.01); G06F 12/0223 (2013.01); G06F 13/1657 (2013.01); H04B 10/2589 (2020.05); H04B 10/40 (2013.01);
Abstract

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.


Find Patent Forward Citations

Nahmias, Mitchell. (2026). Computer architecture with disaggregated memory and high-bandwidth communication interconnects (U.S. Patent No. 12613811). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12613811

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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