Memory controller fractonal bandwidth adjustment for critical and non- critical components

Abstract

A memory controller is provided and configured to control access to a memory with a memory access bandwidth by a plurality of processing components of a data processing system. The memory controller comprises a control unit configured to allocate a respective fraction of the memory access bandwidth to each of the plurality of processing components for accessing the memory by a plurality of memory access operations. Moreover, the memory controller comprises a monitoring unit configured to obtain timing information about a duration of a respective memory access operation by each of the plurality of processing components via a bus of the data processing system. The control unit is further configured to adjust, for one or more of the plurality of processing components, the respective fraction of the memory access bandwidth based on the timing information obtained by the monitoring unit.