The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Oct. 16, 2023
Applicant:

Nanya Technology Corporation, New Taipei City, TW;

Inventor:

Kuo-Hui Su, Taipei City, TW;

Assignee:

NANYA TECHNOLOGY CORPORATION, New Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01); H10P 14/40 (2026.01); H10P 14/60 (2026.01);
U.S. Cl.
CPC ...
H10W 20/089 (2026.01); H10D 62/402 (2025.01); H10D 62/83 (2025.01); H10P 14/416 (2026.01); H10P 14/6308 (2026.01);
Abstract

The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.


Find Patent Forward Citations

Su, Kuo-Hui. (2026). Semiconductor device structure with reduced critical dimension and method for preparing the same (U.S. Patent No. 12610803). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12610803

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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