The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Aug. 25, 2021
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Shogo Ono, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/268 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 21/268 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 24/94 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/26145 (2013.01); H01L 2224/32155 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/94 (2013.01); H01L 2924/1011 (2013.01);
Abstract

The present disclosure relates to a semiconductor chip that allows electrical connections to be protected and a manufacturing method therefor. A semiconductor chip has a strip-shaped region including a plurality of recesses on a side surface thereof. The recesses are arranged in a matrix of rows and columns on the side surface of the semiconductor chip or in a zig-zag pattern in the region. At least two of the strip-shaped regions are formed. The strip-shaped regions are formed in different positions between the vicinity of the center and opposed ends of the side surface. The strip-shaped region is partly inclined. The present disclosure can be applied for example to a semiconductor chip for a semiconductor device in which connections for electrically connecting the semiconductor chip and the substrate are protected with underfill.


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