The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2026
Filed:
Dec. 03, 2020
Applicant:
Vuereal Inc., Waterloo, CA;
Inventors:
Gholamreza Chaji, Waterloo, CA;
Ehsanollah Fathi, Waterloo, CA;
Hossein Zamani Siboni, Waterloo, CA;
Assignee:
VueReal Inc., Waterloo, CA;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10H 20/812 (2025.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H10H 20/00 (2025.01); H10H 20/84 (2025.01); H10H 29/14 (2025.01); H10W 20/20 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10H 20/812 (2025.01); H10H 20/062 (2025.01); H10H 20/84 (2025.01); H10H 29/142 (2025.01); H10W 20/20 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01);
Abstract
The present disclosure relates to a solid state micro device structure that has a microdevice formed on a substrate, with p and n doped layers, active layers between at least the two doped layers, pads coupled to each doped layer, and wherein the n-doped layer is modulated to have a lower conductivity towards an edge of the device. The invention further involves, dielectric layer, conductive layer, passivation layer and MIS structure.