The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Jul. 05, 2022
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventor:

Hiroshi Yoshida, Hsinchu City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2026.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10P 14/60 (2026.01); H10P 50/00 (2026.01); H10P 50/24 (2026.01); H10P 52/40 (2026.01); H10P 76/40 (2026.01); H10P 95/00 (2026.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 64/017 (2025.01); H10D 84/0144 (2025.01); H10D 84/0151 (2025.01); H10P 14/6308 (2026.01); H10P 50/242 (2026.01); H10P 50/692 (2026.01); H10P 52/403 (2026.01); H10P 76/405 (2026.01); H10P 95/062 (2026.01);
Abstract

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.


Find Patent Forward Citations

Loading…