The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Jan. 17, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sangmoon Lee, Suwon-si, KR;

Jinbum Kim, Seoul, KR;

Hyojin Kim, Hwaseong-si, KR;

Yongjun Nam, Hwaseong-si, KR;

Sujin Jung, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 62/113 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01);
Abstract

An integrated circuit (IC) device includes a fin-type active region extending on a substrate in a first lateral direction. A gate line extends on the fin-type active region in a second lateral direction. The second lateral direction intersects the first lateral direction. A channel region is between the substrate and the gate line. A source/drain region is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region. A superlattice barrier is between the substrate and the channel region. The superlattice barrier is in contact with the source/drain region. The superlattice barrier has a structure in which a plurality of first sub-layers including a semiconductor layer doped with oxygen atoms and a plurality of second sub-layers including an undoped semiconductor layer are alternately stacked.


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