The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Jul. 28, 2021
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Koichi Nishi, Tokyo, JP;

Sho Tanaka, Tokyo, JP;

Shinya Soneda, Tokyo, JP;

Kazuya Konishi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 12/00 (2025.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H10D 8/00 (2025.01); H10D 12/01 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01); H10D 84/60 (2025.01);
U.S. Cl.
CPC ...
H10D 12/481 (2025.01); H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H10D 8/422 (2025.01); H10D 12/038 (2025.01); H10D 62/393 (2025.01); H10D 64/112 (2025.01); H10D 64/117 (2025.01); H10D 84/617 (2025.01);
Abstract

In a mesa region sandwiched between adjacent active trenches among mesa regions that are regions each sandwiched between adjacent trenches, a third semiconductor layer has regions discretely arranged in a first direction so as to be in contact with one active trench of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction so as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched between the adjacent active trenches, a fourth semiconductor layer is disposed between the third semiconductor layer on the side in contact with the one active trench and the third semiconductor layer on the side in contact with the other active trench in plan view and between the respective regions of the third semiconductor layer discrete in the first direction.


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