logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12610561 B1

PDFFull Text
Date of Patent:
Apr. 21, 2026

Filed:

Aug. 22, 2023

Method for fabricating a semiconductor device having back gate electrodes, active layers, and data lines

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyungeun Choi, Suwon-si, KR;

Kiseok Lee, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Wael M Fahmy

Assistant Examiner:

Tiberiu Dan Onuta

Int. Cl.
CPC ...
H10B 80/00 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 12/315 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01);
Abstract

A method of fabricating a semiconductor device may use, as an internal contact region, a region in which a memory cell region overlaps a core and/or peripheral region by bonding at least a partial region of the memory cell region to at least a partial region of the core and/or peripheral region by a direct bonding method, and thus, even when an additional contact region is secured outside the memory cell region to be smaller, signals and/or power may be transmitted between the memory cell region and the core and/or peripheral region.

Find Patent Forward Citations

Choi, Hyungeun. (2026). Method for fabricating a semiconductor device having back gate electrodes, active layers, and data lines (U.S. Patent No. 12610561). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12610561

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…