The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Nov. 16, 2023
Applicant:

Nanya Technology Corporation, New Taipei City, TW;

Inventor:

Chih-Wei Huang, Taoyuan City, TW;

Assignee:

NANYA TECHNOLOGY CORPORATION, New Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01);
U.S. Cl.
CPC ...
H10B 12/36 (2023.02); H10B 12/056 (2023.02); H10B 12/485 (2023.02); H10B 12/488 (2023.02); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01);
Abstract

A semiconductor device structure includes a semiconductor substrate, a first fin structure, a first S/D structure, and a bit line contact. The first fin structure is protruding from the semiconductor substrate, and has a first sidewall, a second sidewall, and a top surface connecting the first sidewall to the second sidewall. The first S/D structure is disposed over the first fin structure, and covering the top surface, a portion of the first sidewall, and a portion of the second sidewall of the first fin structure. The bit line contact is disposed over the first S/D structure. The bit line contact includes a barrier layer in contact with the first S/D structure and a conductive layer disposed over the barrier layer.


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