Page buffer related to performing a program operation, memory device including a page buffer, and method of operating the page buffer

Abstract

Provided herein may be a page buffer. The page buffer includes a sensing node connected to a bit line, a bit line voltage controlling circuit configured to precharge the bit line during a verify operation, a sensing node voltage controller configured to precharge the sensing node while the bit line is precharged, a first latch connected to the sensing node, and configured to store a first bit value determined based on a first evaluation operation among bit values corresponding to a voltage level of the sensing node after the sensing node is precharged, and a second latch connected to the sensing node, and configured to store a second bit value determined based on a second evaluation operation after the first bit value is stored. The first latch stores the first bit value determined based on a third evaluation operation after the second bit value is stored in the second latch.