Physical verification workflow for semiconductor circuit designs

Abstract

An electronic design automation (EDA) tool and system for physical verification of workflow for semiconductor circuit designs, and methods of using the same is described. Generally, the method includes (i) automatic splitting an integrated circuit (IC) layout into a number of windows for parallel processing using a plurality of central processing cores; (ii) extracting parasitic capacitance structures from the IC layout; (iii) generating fill elements for masks to fabricate an IC having the IC layout using a metadata matrix to minimize volume of information and resources needed; and (iv) extraction of parasitic resistance structures from IC layout. In some embodiments, the IC layout is additionally or alternatively split into groups of rules for processing. Other embodiments are also described.