The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2026

Filed:

Nov. 20, 2023
Applicant:

Suzhou Metabrain Intelligent Technology Co., Ltd., Suzhou, CN;

Inventors:

Rengang Li, Suzhou, CN;

Hongbin Yang, Suzhou, CN;

Gang Dong, Suzhou, CN;

Dongdong Jiang, Suzhou, CN;

Qichun Cao, Suzhou, CN;

Kekun Hu, Suzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0877 (2016.01); G06F 13/28 (2006.01); G06F 17/16 (2006.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06F 12/0877 (2013.01); G06F 13/28 (2013.01); G06F 17/16 (2013.01); G06N 3/063 (2013.01);
Abstract

Disclosed in the present application are a computing core, an accelerator, a computing method and apparatus, a device, a non-volatile readable storage medium, and a system in the technical field of computers. According to the present application, parallel computing can be performed to obtain matrix multiplication results of N rows of data or N columns of data in a first matrix and N columns of data or N rows of data in a second matrix, so that N final matrix multiplication results may be obtained at one time. And the computing efficiency and speed are improved. The computing core does not need to temporarily store an intermediate result, and are source-on-chip is saved. According to the present application, after the matrix multiplication results are obtained, which memory the matrix multiplication results are stored into can be determined according to a participation manner in which the matrix multiplication results participate in each round of computing in a next matrix multiplication operation, and hence, a storage format of the matrix multiplication results in the memory is consistent with an output format of the matrix multiplication results when participating in computing. Data is conveniently read in sequence in a continuous computing process, and matrix transposition does not need to be carried out. Therefore, the time overhead of accessing a memory can be reduced, and the efficiency is improved.


Find Patent Forward Citations

Li, Rengang. (2026). Computing core, accelerator, computing method and apparatus, device, non-volatile readable storage medium, and system (U.S. Patent No. 12608319). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12608319

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