Low latency crosstalk mitigation in a nonvolatile memory

Abstract

A storage system includes circuitry and memory cells that are coupled to multiple WLs and to multiple BLs. The circuitry includes combinational logic, and is configured to: set a read voltage to a target WL, and set each of the other WLs, including a neighbor WL neighboring to the target WL, to a predefined full conducting voltage or to a predefined partial conducting voltage lower than the full conducting voltage, pre-charge the BLs, and while discharging the BLs, read a page from a group of target memory cells multiple times, to produce multiple respective binary readouts, at least one of the readouts corresponds to setting the neighbor WL to the partial conducting voltage, apply the combinational logic to the readouts to produce (i) output bits of the page, and (ii) confidence levels associated with the output bits, and transmit the output bits and the confidence levels to a controller.