The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2026
Filed:
Feb. 24, 2023
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Jais Abraham, Bangalore, IN;
Arvind Jain, San Diego, CA (US);
Rajeev Komalan Nair, Bangalore, IN;
Basim Mohammed Issa Shanyour, San Diego, CA (US);
Madan Krishnappa, San Diego, CA (US);
Assignee:
Qualcomm Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318536 (2013.01); G01R 31/31723 (2013.01); G01R 31/31724 (2013.01); G01R 31/31725 (2013.01); G01R 31/318555 (2013.01); G01R 31/318558 (2013.01); G06F 13/4022 (2013.01);
Abstract
Scan testing features on a chip may include a streaming scan network (SSN) with core streaming scan hubs (CSHs). A CSH may include a parent bus interface, a child bus interface, and a streaming scan hub (SSH). A CSH may also include multiplexing logic configured to select whether the child bus interface is included in the SSN or excluded from the SSN. Multiple CSHs may be interconnected in a hierarchical topology through the child bus interfaces.