The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2026
Filed:
Aug. 10, 2023
Qualcomm Incorporated, San Diego, CA (US);
Amit Aneja, Chandler, AZ (US);
Dipti Ranjan Pal, Irvine, CA (US);
Kiran Kumar Malipeddi, San Diego, CA (US);
Qualcomm Incorporated, San Diego, CA (US);
Abstract
Methods and apparatuses directed to. In some examples, a die package includes voltage logic that provides a voltage to a voltage rail, clock logic that generates a clock signal, and adaptive clock distribution logic that receives the clock signal and the voltage. The adaptive clock distribution logic can increment an event count when the clock signal is above a threshold frequency, or when the voltage is below a threshold voltage level. The die package also includes a processor that can monitor the event counts during operation and determine a status of the adaptive clock distribution logic based on the event counts. In some examples, the processor can test the adaptive clock distribution logic by causing the clock signal to operate above the threshold frequency, or causing the voltage logic to provide the voltage below the threshold voltage level. The processor can then read the event counts to determine the status.