The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

Oct. 03, 2022
Applicant:

Shanghai Biren Technology Co., Ltd, Shanghai, CN;

Inventors:

Shiqun Gu, Shanghai, CN;

Zhou Hong, Shanghai, CN;

Linglan Zhang, Shanghai, CN;

Zheng Tian, Shanghai, CN;

Hongying Zhang, Shanghai, CN;

Peng Liu, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H10D 1/68 (2025.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 23/3157 (2013.01); H01L 23/49811 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/80 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H10D 1/68 (2025.01); H01L 24/05 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/80424 (2013.01); H01L 2224/80447 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/81 (2013.01);
Abstract

The present disclosure provides a chipset and a manufacturing method thereof. The chipset includes a logic chip, an input/output chip, and an interposer. The logic chip includes a plurality of first bonding components disposed in the first device layer. The input/output chip includes a plurality of second bonding components disposed in the second device layer. The interposer includes a plurality of third bonding components disposed in the third device layer. The logic chip is directly bonded to the first portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through the first portion of the plurality of first bonding components, and the input/output chip is directly bonded to the second portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through the plurality of second bonding components.


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