The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

Dec. 06, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sohye Cho, Hwaseong-si, KR;

Kwangjin Moon, Hwaseong-si, KR;

Hojin Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); B82Y 10/00 (2011.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/485 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01);
Abstract

A semiconductor device includes a first semiconductor substrate having a protruding active pattern, a gate structure, a source/drain region in the active pattern on a side of the gate structure, an interlayer insulating layer on the source/drain region, a contact structure connected to the source/drain region through the interlayer insulating layer, a through-via structure electrically connected to the contact structure and passing through the interlayer insulating layer and the first semiconductor substrate, a first bonding structure including a first insulating layer on the first semiconductor substrate and a first connection pad in the first insulating layer, a second bonding structure on the first bonding structure and including a second insulating layer bonded to the first insulating layer and a second connection pad in the second insulating layer and bonded to the first connection pad, and a second semiconductor substrate disposed on the second bonding structure.


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