logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12604652 B1

PDFFull Text
Date of Patent:
Apr. 14, 2026

Filed:

Jan. 07, 2022

Method for manufacturing display device, display device, display module, and electronic device

Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Shunpei Yamazaki, Setagaya, JP;

Takayuki Ikeda, Atsugi, JP;

Kenichi Okazaki, Atsugi, JP;

Yasumasa Yamane, Atsugi, JP;

Hajime Kimura, Atsugi, JP;

Tatsuya Onuki, Atsugi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Attorneys:

Eric J. Robinson

Robinson Intellectual Property Law Office, P.C.

Primary Examiner:

Anne M Hines

Assistant Examiner:

Jose M Diaz

Int. Cl.
CPC ...
H10K 71/20 (2023.01); H10K 50/19 (2023.01); H10K 59/131 (2023.01); H10K 59/35 (2023.01); H10K 59/80 (2023.01); H10K 71/16 (2023.01); H10K 71/60 (2023.01);
U.S. Cl.
CPC ...
H10K 71/231 (2023.02); H10K 50/19 (2023.02); H10K 59/353 (2023.02); H10K 71/166 (2023.02); H10K 71/60 (2023.02); H10K 59/131 (2023.02); H10K 59/871 (2023.02); H10K 59/8722 (2023.02); H10K 59/8723 (2023.02); H10K 59/873 (2023.02);
Abstract

A high-resolution or high-definition display device is provided. The display device is manufactured by forming a first pixel electrode and a second pixel electrode; forming a first layer over the first pixel electrode and the second pixel electrode; forming a first sacrificial layer over the first layer; processing the first layer and the first sacrificial layer to expose at least part of the second pixel electrode; forming a second layer over the first pixel electrode and the second pixel electrode; forming a second sacrificial layer over the second layer; processing the second layer and the second sacrificial layer to expose at least part of the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; forming a third layer over the first pixel electrode and the second pixel electrode; forming a counter electrode over the third layer; and processing the third layer and the counter electrode to remove at least part of each of the third layer and the counter electrode included in a region between the first pixel electrode and the second pixel electrode in a top view.

Find Patent Forward Citations

Loading…