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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12604507 B1

PDFFull Text
Date of Patent:
Apr. 14, 2026

Filed:

Mar. 16, 2023

Method of manufacturing semiconductor device

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Futoshi Komatsu, Tokyo, JP;

Tomoo Nakayama, Tokyo, JP;

Katsuhiro Uchimura, Tokyo, JP;

Hiroshi Inagawa, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Tokyo, JP;

Attorney:

Rimon P.C.

Primary Examiner:

Victor A Mandala

Assistant Examiner:

Colleen E Snow

Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/02 (2006.01); H01L 21/288 (2006.01); H01L 21/304 (2006.01); H01L 21/56 (2006.01); H10D 12/01 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02359 (2013.01); H01L 21/288 (2013.01); H01L 21/304 (2013.01); H01L 21/56 (2013.01); H10D 12/038 (2025.01); H10D 64/513 (2025.01);
Abstract

A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.

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