The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

Apr. 18, 2024
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventor:

Semyon Lebedev, Ottawa, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01);
Abstract

Provided is a track and hold circuit. The track and hold circuit includes: a CMOS FVF; a pair of first switches, each of the first switches being coupled between a corresponding one of differential signal inputs and a corresponding one of differential inputs of the FVF; a second switch coupled between differential outputs of the FVF; the FVF includes a pair of first transistors with gates being differential inputs of the FVF and sources being the differential outputs of the FVF, a pair of second transistors, a first current mirror transistor, a second current mirror transistor and a third switch; where a state of the second switch is controlled by a clock signal to be the same as a state of the first switches, and a state of the third switch is controlled to be complementary to the state of the second switch.


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