The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

Apr. 25, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sangsoo Cha, Suwon-si, KR;

Minjeong Kwon, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 16/34 (2006.01); G11C 29/04 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G06F 3/0604 (2013.01); G06F 3/061 (2013.01); G06F 3/0614 (2013.01); G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G11C 16/3495 (2013.01); G11C 29/52 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7204 (2013.01); G06F 2212/7205 (2013.01); G06F 2212/7208 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A memory controller includes a health grade determining circuit to determine a health grade of a memory block based on a combination of an error detecting result of data read from at least one page of the block and block information related to a degree of degradation of the block, and an IO ratio setting circuit. The IO ratio setting circuit sets, according to the determined health grade, an IO ratio between a host IO operation and an internal IO operation. The host IO operation exchanges data with the memory device in response to a request from a host and the internal IO operation exchanges data with the memory device in relation to a background operation. The memory controller performs the host IO operation and the internal IO operation with the memory device according to the set IO ratio during a period in which the background operation is performed.


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