The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

Nov. 08, 2023
Applicants:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Centre National DE LA Recherche Scientifique, Paris, FR;

Universite D'aix-marseille, Marseilles, FR;

Inventors:

Mona Ezzadeen, Grenoble, FR;

François Andrieu, Grenoble, FR;

Jean-Michel Portal, Saint Savournin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/10 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/10 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A data storage circuit of NOR type includes a three-dimensional memory structure, produced on a first semiconductor substrate, and comprising a plurality of memory planes, each plane forming a two-dimensional array of memory cells. Each memory cell has a selection node, a first input/output node and a second input/output node. The three-dimensional memory structure has an upper surface comprising a plurality of connectors distributed over the surface; each connector is connected to at least one among the first or second input/output nodes of a given column; a control circuit produced on a second semiconductor substrate; an interconnection structure comprising: a plurality of bonding pads placed between the control circuit and the upper surface; the plurality of bonding pads forms a periodic repetition of a unit pattern in a plane parallel to the upper surface.


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