The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2026

Filed:

Nov. 28, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Mihir Narendra Mody, Bangalore, IN;

Niraj Nandan, Plano, TX (US);

Hetul Sanghvi, Richardson, TX (US);

Manoj Koul, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/03 (2006.01); G06F 11/07 (2006.01); G06V 10/36 (2022.01); G06V 10/98 (2022.01); G06T 7/00 (2017.01); H04L 41/0677 (2022.01);
U.S. Cl.
CPC ...
G06V 10/98 (2022.01); G06F 11/0736 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 11/079 (2013.01); G06V 10/36 (2022.01); G06T 7/0002 (2013.01); H04L 41/0677 (2013.01);
Abstract

Systems and articles of manufacture provide an efficient safety mechanism for signal processing hardware. An example system includes a hardware accelerators, including a first hardware accelerator, and a second hardware accelerator coupled to the first hardware accelerator. Each of the first and second hardware accelerators includes a protected memory and an unprotected memory, and at least one of the hardware accelerators has an outlier filter. The system also includes a memory coupled to the hardware accelerators; and interface protectors, including a first interface protector coupled between the first hardware accelerator and the memory; a second interface protector coupled between the first hardware accelerator, the memory, and the second hardware accelerator; and a third interface protector coupled between the second hardware accelerator and the memory.


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