Register clock driver, operating method of register clock driver, and memory module including register clock driver and plurality of memory devices

Abstract

Disclosed is a register clock driver which includes an operating circuit that buffers a command and an address received from an external memory controller, and a training circuit that performs a first training operation and a second training operation in an initialization operation. In the first training operation, one of a plurality of reference clock signals is selected as a first training clock signal for sampling output signals output from the operating circuit. In the second training operation, a second training clock signal for sampling the output signals is selected through phase adjustment based on the first training clock signal.