The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

May. 26, 2021
Applicant:

Lg Innotek Co., Ltd., Seoul, KR;

Inventors:

Nam Heon Kim, Seoul, KR;

Chang Je Kim, Seoul, KR;

Seong Hwan Im, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/13 (2006.01); H01L 23/485 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 23/485 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01);
Abstract

A package substrate according to an embodiment includes a first substrate; and a first chip mounted on the first substrate; wherein the first substrate includes: a first insulating layer including a first region overlapping the first chip in a vertical direction and a second region other than the first region; and a circuit pattern disposed on the first region and the second region of the first insulating layer; wherein the circuit pattern includes: a pad portion including a first portion disposed on an upper surface of the second region of the first insulating layer, a second portion buried in the first region of the first insulating layer, and a third portion including at least a part buried in the first region of the first insulating layer and connecting between the first portion and the second portion; wherein at least a part of the first chip is disposed in the first region of the first insulating layer; wherein the first region of the first insulating layer surrounds a lower surface and a side surface of the first chip, and wherein the first region and the second region of the first insulating layer are a single insulating layer.


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