The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Mar. 01, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brent Anderson, Jericho, VT (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Kisik Choi, Watervliet, NY (US);

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Christopher J. Penny, Saratoga Springs, NY (US);

Robert Robison, Rexford, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/02362 (2013.01); H01L 21/02697 (2013.01); H01L 21/0475 (2013.01); H01L 21/31053 (2013.01);
Abstract

A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.


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