The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Feb. 08, 2023
Applicant:

GE Aviation Systems Llc, Grand Rapids, MI (US);

Inventors:

Collin William Hitchcock, Clifton Park, NY (US);

Stacey J. Kennerly, Niskayuna, NY (US);

Ljubisa D. Stevanovic, Clifton Park, NY (US);

Assignee:

GE AVIATION SYSTEMS LLC, Grand Rapids, MI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H10D 62/109 (2025.01); H10D 62/127 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01);
Abstract

A semiconductor device cell includes a JFET region adjacent a channel region, the JFET region defining a periphery of the semiconductor device cell. The JFET region includes a first corner region and a second corner region separated by a JFET intermediate region. A first width of the JFET intermediate region extending from an edge of the JFET intermediate region abutting a periphery of the channel region to the periphery of the semiconductor device cell is greater than a second width of the JFET region extending from an edge of at least one of the first corner region and the second corner region abutting the periphery of the channel region to the semiconductor cell periphery.


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