The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Mar. 27, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Donghoon Kwon, Suwon-si, KR;

Beomjin Park, Suwon-si, KR;

Boun Yoon, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device includes a substrate, circuit devices on the substrate, lower interconnection lines electrically connected to the circuit devices, a peripheral region insulating layer covering the lower interconnection lines, a source structure on the peripheral region insulating layer, gate electrodes stacked and spaced apart from each other in a first direction on the source structure, channel structures penetrating through the gate electrodes and each including a channel layer, contact plugs penetrating through the gate electrodes and the source structure, extending in the first direction, and connected to a portion of the lower interconnection lines, and spacer layers between the contact plugs and the source structure and including a material different from a material of the insulating layer in the peripheral region, wherein each of the spacer layers has a first width on an upper surface and has a second width greater than the first width on a lower surface.


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