The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Aug. 30, 2024
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Peter Normand Labrecque, Austin, TX (US);

Sayan Ganguly, Austin, TX (US);

Samer Ghanem, Austin, TX (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01); H03K 3/3562 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 3/0372 (2013.01); H03K 3/356191 (2013.01); H03K 3/35625 (2013.01);
Abstract

An apparatus, including: a level shifter configured to: receive an input data signal in a first voltage domain; receive a reset signal in a second voltage domain; and generate an intermediate signal in the second voltage domain based on the input data signal and the reset signal; and a resettable latch configured to generate an output signal in the second voltage domain at an output in response to receiving the input data signal, the intermediate signal, the reset signal, and a clock signal in the second voltage domain, the output signal being based on logic states of the input data signal, the intermediate signal, the reset signal, and the clock signal, respectively.


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