The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Nov. 30, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sooryong Lee, Seoul, KR;

Jaewon Yang, Suwon-si, KR;

Kyoung Cho Na, Hwaseong-si, KR;

Jihong Kim, Seongnam-si, KR;

Sang Chul Yeo, Osan-si, KR;

Hyeok Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/00 (2017.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 115/02 (2020.01); G06N 20/00 (2019.01); G06T 3/40 (2006.01); G06T 11/00 (2006.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
G06T 7/001 (2013.01); G06F 30/392 (2020.01); G06T 3/40 (2013.01); G06T 11/00 (2013.01); G06T 2207/20081 (2013.01); G06T 2207/30148 (2013.01);
Abstract

Disclosed is an operating method of an electronic device which includes a processor executing a semiconductor layout simulation module based on machine learning. The operating method includes receiving, at the semiconductor layout simulation module executed by the processor, a layout image, inferring a wafer image based on the layout image and a fabrication device information image of a semiconductor fabrication device fabricating a semiconductor integrated circuit based on a final layout image, adjusting the layout image when the wafer image is not acceptable, and confirming the layout image as the final layout image when the wafer image is acceptable.


Find Patent Forward Citations

Lee, Sooryong. (2026). Operating method of electronic device including processor executing semiconductor layout simulation module based on machine learning (U.S. Patent No. 12597119). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12597119

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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