The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2026

Filed:

Sep. 02, 2022
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ian Tramble, Mountain View, CA (US);

Akash Bellubbi, San Jose, CA (US);

Ashutosh Tadkase, Los Altos Hills, CA (US);

Peter Boonstoppel, Pleasanton, CA (US);

Suraj Das, Santa Clara, CA (US);

Ranvijay Singh, Santa Clara, CA (US);

Sever Topan, Burnaby, CA;

Albert Davies, San Jose, CA (US);

Linda Xiong, Milpitas, CA (US);

Sharat Janapareddy, San Jose, CA (US);

Ashkan Vafaee, Austin, TX (US);

John Lore, San Jose, CA (US);

Ian Howson, Santa Clara, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 11/07 (2006.01); G06F 21/52 (2013.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/30087 (2013.01); G06F 9/3836 (2013.01); G06F 9/485 (2013.01); G06F 9/5055 (2013.01); G06F 9/5083 (2013.01); G06F 9/544 (2013.01); G06F 11/0721 (2013.01); G06F 11/0757 (2013.01); G06F 21/52 (2013.01); G06F 2221/2151 (2013.01);
Abstract

One or more embodiments of the present disclosure relate to receiving application data indicative of a plurality of runnables corresponding to a computing application. Additionally, one or more embodiments may relate to generating, based at least on the application data, an execution schedule for execution of the plurality of runnables using a plurality of compute engines. The execution schedule may include one or more commands corresponding to one or more timing fences. The one or more timing fences may dictate a timing and order of execution between at least a first runnable and a second runnable of the plurality of runnables.


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