The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Jan. 23, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Ravi Keshav Joshi, Klagenfurt am Wörthersee, AT;

Thomas Ralf Siemieniec, Villach, AT;

Werner Schustereder, Villach, AT;

Kristijan Luka Mletschnig, Klagenfurt, AT;

Axel König, Villach, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/13 (2025.01); H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 62/832 (2025.01); H10D 64/23 (2025.01); H10D 64/62 (2025.01);
U.S. Cl.
CPC ...
H10D 62/155 (2025.01); H01L 21/0475 (2013.01); H01L 21/0485 (2013.01); H10D 12/031 (2025.01); H10D 30/668 (2025.01); H10D 62/8325 (2025.01); H10D 64/252 (2025.01); H10D 64/62 (2025.01);
Abstract

A method of manufacturing a semiconductor device includes forming a trench that extends from a first surface into a silicon carbide body. A first doped region and an oppositely doped second doped region are formed in the silicon carbide body. A lower layer structure is formed on a lower sidewall portion of the trench. An upper layer stack is formed on an upper sidewall portion and/or on the first surface. The first doped region and the upper layer stack are in direct contact along the upper sidewall portion and/or on the first surface. The second doped region and the lower layer structure are in direct contact along the lower sidewall portion.


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