Vertically stacked memory device and manufacturing method thereof

Abstract

The present disclosure discloses a vertical stack-type memory device may including a word line extending in a horizontal direction and having a vertical through-hole region, a vertical bit line arranged vertically to pass through the through-hole region, a channel layer pattern arranged to surround the vertical bit line inside the through-hole region, a body insulating layer disposed between the vertical bit line and a remaining portion except for the one end of the channel layer pattern, an electrode member arranged to surround an outer peripheral surface of the channel layer pattern at a height higher than the word line, a dielectric layer pattern disposed between the word line and the channel layer pattern and having a structure surrounding the electrode member, and a plate electrode in contact with the dielectric layer pattern above the word line.