Interleaved page buffers for inputting and outputting data with memory latches and status registers including a memory device

Abstract

Provided herein is a memory device for inputting and outputting data and a memory system including the memory device and a memory controller. The memory device includes memory cells, a plurality of latches configured to sense a plurality of pieces of logical page data stored in the memory cells, and an operation controller configured to output a first latch select signal for selecting first latches, by which first logical page data among the plurality of pieces of logical page data is sensed, from among the plurality of latches in response to a first page data output command. The first latches output the first logical page data in response to the first latch select signal.