The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2026

Filed:

Aug. 13, 2024
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Ming-Hung Wu, Nantou County, TW;

Wei-Chen Chen, Taoyuan City, TW;

Hang-Ting Lue, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/11582 (2017.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 99/00 (2023.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 99/20 (2023.02);
Abstract

Provided are a 3D memory and an operating method thereof. In the 3D memory, a stacked structure includes gate layers and insulating layers alternately stacked. Each gate layer includes first and second gates spaced from each other. Each annular channel layer corresponds to one of the gate layers and is disposed between adjacent insulating layers. A p-type doping region is disposed in each channel layer and adjacent to the first gate. An n-type doped region is disposed in each channel layer and adjacent to the second gate. A source line pillar penetrates through the stacked structure and contacts the n-type doped region. A bit line pillar penetrates through the stack structure and contacts the p-type doped region. A first gate insulation layer is disposed between the first gate and the channel layer. A second gate insulation layer is disposed between the second gate and the channel layer.


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