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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12592264 B1

PDFFull Text
Date of Patent:
Mar. 31, 2026

Filed:

Jun. 28, 2024

Reduction in chip area through design-technology co-optimization

Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Ankit Rehani, Burari, IN;

Chao Qin, Foster City, CA (US);

Mohan Vamsi Dunga, Santa Clara, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:

Pearl Cohen Zedek Latzer Baratz LLP

Primary Examiner:

Pho M Luu

Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 5/14 (2006.01); G11C 11/404 (2006.01); G11C 11/4096 (2006.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 41/20 (2023.01); H10B 41/50 (2023.01); H10B 43/20 (2023.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
G11C 5/146 (2013.01); G11C 11/4045 (2013.01); G11C 11/4096 (2013.01); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 41/20 (2023.02); H10B 41/50 (2023.02); H10B 43/20 (2023.02); H10B 43/50 (2023.02);
Abstract

Multi-stage charge pumps use a modular structure in which each stage include a pair of legs, or current paths, between the stage input and the stage output. Each leg includes a stage boosting capacitor having a first plate connected to the current path and a second plate connected to receive one of a pair of non-overlapping clock signals. Each leg has an NMOS charge transfer switch connected between the stage input and the first plate of the stage boosting capacitor and a PMOS charge transfer switch connected between the first plate of the stage boosting capacitor and the stage output. To reduce charge pump area, the NMOS and PMOS charge transfer switches are formed to have a same resistance value when in an on state, where to achieve this the NMOS charge transfer switches are formed with wider control gates than the PMOS charge transfer switches.

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