Automated synthesis of virtual system-on-chip environments

Abstract

The present disclosure presents systems and methods performing a simulation on a hybrid virtual system-on-chip (SoC) model. One such method comprises receiving a configuration file that identifies register transfer level (RTL) abstractions; virtual prototype abstractions; unit-level testbenches; place holder variables; and a shared interface among one or more hardware circuitry blocks designed as RTL abstractions and one or more hardware circuitry blocks designed as virtual prototype abstractions; creating the hybrid virtual SoC model based on the configuration file by instantiating the one or more hardware circuitry blocks designed as RTL abstractions and a stub hardware circuitry block for each of the one or more hardware circuitry blocks designed as virtual prototype abstractions; and integrating unit-level testbenches for the one or more hardware circuitry blocks represented as RTL abstractions.