The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2026
Filed:
Feb. 06, 2024
Infineon Technologies Llc, San Jose, CA (US);
Sergey Ostrikov, Redwood City, CA (US);
Infineon Technologies LLC, San Jose, CA (US);
Abstract
An integrated circuit includes an array of flash memory and flash translation layer (FTL) logic coupled to the array and to be coupled to a host device. The FTL logic is configured to receive, from the host device, a write command comprising a first logical address, user data, and an access token and translate the first logical address to a first physical address of the array. In an embodiment, the first physical address has already been programmed. The FTL logic is further to verify the access token as being associated with the first logical address, cause the user data to be programmed to a second physical address of the array, and update at least one logical-to-physical (L2P) mapping table with the second physical address as being mapped to the first logical address.