The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Dec. 21, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yeongbeom Ko, Suwon-si, KR;

Junyun Kweon, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/561 (2013.01); H01L 23/3107 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 24/05 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/94 (2013.01);
Abstract

A semiconductor package includes at least one semiconductor module on a substrate. The semiconductor module includes a first semiconductor chip having a first surface and a second surface opposite to the first surface, a second semiconductor chip on the first surface, a plurality of conductive pillars on the first surface, and a redistribution substrate on the second semiconductor chip and the plurality of conductive pillars. The redistribution substrate has a third surface and a fourth surface opposite to the third surface. The third surface of the redistribution substrate faces the first surface of the first semiconductor chip, the plurality of conductive pillars are electrically connected to the first surface of the first semiconductor chip and the third surface of the redistribution substrate, and the fourth surface of the redistribution substrate is electrically connected to the substrate of the semiconductor package.


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