The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Jul. 27, 2023
Applicant:

Nec Corporation, Tokyo, JP;

Inventors:

Katsumi Kikuchi, Tokyo, JP;

Akira Miyata, Tokyo, JP;

Suguru Watanabe, Tokyo, JP;

Takanori Nishi, Tokyo, JP;

Hideyuki Satou, Tokyo, JP;

Kenji Nanba, Tokyo, JP;

Ayami Yamaguchi, Tokyo, JP;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); G06N 10/40 (2022.01); H01L 23/13 (2006.01); H01L 23/36 (2006.01); H01L 23/367 (2006.01); H10N 60/81 (2023.01); H10N 69/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49888 (2013.01); G06N 10/40 (2022.01); H01L 23/13 (2013.01); H01L 23/3677 (2013.01); H10N 60/815 (2023.02); H10N 69/00 (2023.02); H01L 23/36 (2013.01);
Abstract

A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device includes a quantum chip and an interposer on which the quantum chip is located. The interposer includes an interposer substrate and an interposer wiring layer. The interposer wiring layer is disposed on a surface of the interposer substrate on a side on which the quantum chip is located. The interposer wiring layer includes, in at least a part thereof, a superconducting material layer formed of a superconducting material and a non-superconducting material layer formed of a non-superconducting material.


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